| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2023-12-13 | Added some tests for xor and or gates and also added comments to explain how ↵HEADmaster | omagdy7 | 1 | -49/+23 | |
| some functions work and what they do and changed some functions return type to slices instead of borrowed references to owned types for more idomatic rust code | |||||
| 2023-11-29 | Added full implementation of simulating a Chip | omagdy7 | 1 | -26/+40 | |
| 2023-11-27 | Added dfs traversal of gates graph | omagdy7 | 1 | -38/+12 | |
| 2023-11-27 | Added the intial design of the logic gate simulator | omagdy7 | 1 | -42/+67 | |
| 2023-08-18 | Cleaned the code + added output_layer for displaying outputs | omagdy7 | 1 | -3/+9 | |
| 2023-08-11 | Added an InputPanel to the left | omagdy7 | 1 | -15/+23 | |
| 2023-08-10 | Intial commit | omagdy7 | 1 | -0/+38 | |
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index : lgsim | |
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