Added dfs traversal of gates graph

1 files changed, 12 insertions, 38 deletions

diff --git a/src/main.rs b/src/main.rs
index a70ace9..9acda46 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,4 +1,5 @@
 #![allow(dead_code)]
+mod circuit;
 mod gate;
 mod pin;
 mod types;
@@ -7,34 +8,9 @@ use crate::pin::*;
 use crate::types::*;
 use std::vec;
 
-// Define a struct to represent the Circuit
-#[derive(Debug, Clone)]
-struct Circuit {
-    chips: Chips,
-}
-
-impl Circuit {
-    fn new() -> Circuit {
-        Circuit { chips: Vec::new() }
-    }
-
-    fn add_chip(&mut self, chip: Chip) -> usize {
-        self.chips.push(chip);
-        0
-    }
-
-    fn connect_chip(&mut self, from: usize, to: usize) {
-        todo!()
-    }
-
-    fn simulate(&mut self) {
-        todo!();
-    }
-}
-
 fn main() {
     let mut _chip = Chip::new();
-    let a: u8 = 1;
+    let a: u8 = 0;
     let b: u8 = 1;
     let input: Vec<PinValue> = vec![a, b];
     println!("input: {:?}", input);
@@ -58,18 +34,16 @@ fn main() {
     xor.connect_gate(&mut gate_6, &mut gate_7, 1);
     xor.connect_gate(&mut gate_7, &mut gate_8, 0);
 
-    // let dag = xor.gate_dag();
-    let mut sorted = xor.pins();
-    sorted.sort_by(|&x, &y| x.id.cmp(&y.id));
-
-    // println!("pins: {:#?}", sorted);
-    // println!("connections: {:#?}", xor.connections);
-    // println!("dag: {:#?}", dag);
-    println!(
-        "Gate: {:?}\n output = {:?}",
-        &mut gate_8.evaluate(),
-        gate_8.clone(),
-    );
+    let dag = xor.gate_dag();
+    // println!("pins: {:#?}", xor.pins());
+    println!("dag: {:#?}", dag);
+    // println!("dag: {:#?}", xor.gates);
+    // xor.simulate();
+    // println!(
+    //     "Output: {:?}\n Gate = {:?}",
+    //     &mut gate_8.evaluate(),
+    //     gate_8.clone(),
+    // );
 }
 
 // #[macroquad::main("lgsim")]