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| author | omagdy7 <omar.professional8777@gmail.com> | 2023-11-27 13:45:48 +0200 |
|---|---|---|
| committer | omagdy7 <omar.professional8777@gmail.com> | 2023-11-27 13:45:48 +0200 |
| commit | 7ccc460a99bdd6299af9fc95d246826715092df1 (patch) | |
| tree | ad885618b9887f0145e81c7f89af3bd5cc1295ae /src/types.rs | |
| parent | 1e5dc994b7c7317a8c5be5c600dcd2dc90b0ac07 (diff) | |
| download | lgsim-7ccc460a99bdd6299af9fc95d246826715092df1.tar.xz lgsim-7ccc460a99bdd6299af9fc95d246826715092df1.zip | |
Added the intial design of the logic gate simulator
Diffstat (limited to 'src/types.rs')
| -rw-r--r-- | src/types.rs | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/types.rs b/src/types.rs new file mode 100644 index 0000000..5425649 --- /dev/null +++ b/src/types.rs @@ -0,0 +1,9 @@ +use crate::gate::*; +use crate::pin::*; +use std::collections::HashMap; + +pub type PinValue = u8; +pub type Pins = Vec<Pin>; +pub type Gates = Vec<Gate>; +pub type Chips = Vec<Chip>; +pub type Connections = HashMap<Pin, Vec<Pin>>; |