| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2023-11-29 | Changed Chip structure and added pins which represents the chips input pins ↵ | omagdy7 | 1 | -4/+6 | |
| and output pins and added input and output to reference th ids of those input and output pins | |||||
| 2023-11-29 | Removed Or and Buffer Gate implementations and added the same logic of ↵ | omagdy7 | 1 | -49/+74 | |
| AndGate to the NotGate | |||||
| 2023-11-29 | Changed Added pins to AddGate that represents all the and Gate pins and made ↵ | omagdy7 | 1 | -17/+26 | |
| input and output reference pins ids and modified the evaluate function accordingly | |||||
| 2023-11-29 | Removed uncessary Or and Buffer gates | omagdy7 | 1 | -51/+44 | |
| 2023-11-29 | Changed some types definitions | omagdy7 | 1 | -2/+2 | |
| 2023-11-27 | Added dfs traversal of gates graph | omagdy7 | 3 | -65/+106 | |
| 2023-11-27 | Added the intial design of the logic gate simulator | omagdy7 | 8 | -196/+561 | |
| 2023-08-18 | Cleaned the code + added output_layer for displaying outputs | omagdy7 | 4 | -31/+70 | |
| 2023-08-11 | Added an InputPanel to the left | omagdy7 | 5 | -28/+82 | |
| 2023-08-10 | Intial commit | omagdy7 | 2 | -0/+149 | |
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index : lgsim | |
| Unnamed repository; edit this file 'description' to name the repository. |
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