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| author | omagdy7 <omar.professional8777@gmail.com> | 2023-11-29 00:11:39 +0200 |
|---|---|---|
| committer | omagdy7 <omar.professional8777@gmail.com> | 2023-11-29 00:11:39 +0200 |
| commit | fb4ba46a7fa9055a7848d8e0fa3daed2ce0b014f (patch) | |
| tree | 08fbbbc71330fc18e30cf334a92c16135247e4dd /src | |
| parent | 9140fcedde3c0316852f9bab3598a1570415b085 (diff) | |
| download | lgsim-fb4ba46a7fa9055a7848d8e0fa3daed2ce0b014f.tar.xz lgsim-fb4ba46a7fa9055a7848d8e0fa3daed2ce0b014f.zip | |
Changed Chip structure and added pins which represents the chips input pins and output pins and added input and output to reference th ids of those input and output pins
Diffstat (limited to 'src')
| -rw-r--r-- | src/gate.rs | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/gate.rs b/src/gate.rs index b42a125..3925a45 100644 --- a/src/gate.rs +++ b/src/gate.rs @@ -291,8 +291,9 @@ impl NotGate { pub struct Chip { pub gates: Gates, pub connections: Connections, - input: Pins, - output: Pins, + pins: HashMap<usize, Pin>, + input: Vec<usize>, + output: Vec<usize>, } impl Chip { @@ -300,8 +301,9 @@ impl Chip { Chip { gates: Gates::new(), connections: HashMap::new(), - input: Pins::new(), - output: Pins::new(), + pins: HashMap::new(), + input: vec![], + output: vec![], } } |
