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authoromagdy7 <omar.professional8777@gmail.com>2023-11-27 16:27:46 +0200
committeromagdy7 <omar.professional8777@gmail.com>2023-11-27 16:27:46 +0200
commit3eceea8dbcb0743258ab7b3bc7ca90477c81f40d (patch)
treecb43ff97b6c7c94f0b53fbb75a64b1dcc8652d9c /src/circuit.rs
parent7ccc460a99bdd6299af9fc95d246826715092df1 (diff)
downloadlgsim-3eceea8dbcb0743258ab7b3bc7ca90477c81f40d.tar.xz
lgsim-3eceea8dbcb0743258ab7b3bc7ca90477c81f40d.zip
Added dfs traversal of gates graph
Diffstat (limited to 'src/circuit.rs')
-rw-r--r--src/circuit.rs25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/circuit.rs b/src/circuit.rs
new file mode 100644
index 0000000..6882296
--- /dev/null
+++ b/src/circuit.rs
@@ -0,0 +1,25 @@
+use crate::{gate::Chip, types::*};
+
+#[derive(Debug, Clone)]
+struct Circuit {
+ chips: Chips,
+}
+
+impl Circuit {
+ fn new() -> Circuit {
+ Circuit { chips: Vec::new() }
+ }
+
+ fn add_chip(&mut self, chip: Chip) -> usize {
+ self.chips.push(chip);
+ 0
+ }
+
+ fn connect_chip(&mut self, from: usize, to: usize) {
+ todo!()
+ }
+
+ fn simulate(&mut self) {
+ todo!();
+ }
+}