From 7ccc460a99bdd6299af9fc95d246826715092df1 Mon Sep 17 00:00:00 2001
From: omagdy7 <omar.professional8777@gmail.com>
Date: Mon, 27 Nov 2023 13:45:48 +0200
Subject: Added the intial design of the logic gate simulator

---
 src/pin.rs | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 src/pin.rs

(limited to 'src/pin.rs')

diff --git a/src/pin.rs b/src/pin.rs
new file mode 100644
index 0000000..2602d26
--- /dev/null
+++ b/src/pin.rs
@@ -0,0 +1,41 @@
+use crate::types::*;
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
+pub enum PinType {
+    Undetermined,
+    ChipInput,
+    GateInput,
+    GateOutput,
+    ChipOutput,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
+pub struct Pin {
+    pub id: usize,
+    pub kind: PinType,
+    pub gate_id: usize,
+    pub val: Option<PinValue>,
+}
+
+impl Pin {
+    pub fn new(kind: PinType, gate_id: usize, val: PinValue) -> Self {
+        static mut ID: usize = 0;
+        unsafe {
+            ID += 1;
+            match kind {
+                PinType::Undetermined => Pin {
+                    id: ID,
+                    gate_id,
+                    kind,
+                    val: None,
+                },
+                _ => Pin {
+                    id: ID,
+                    gate_id,
+                    kind,
+                    val: Some(val),
+                },
+            }
+        }
+    }
+}
-- 
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