summaryrefslogtreecommitdiff
path: root/src/gate.rs
AgeCommit message (Collapse)AuthorFilesLines
2023-11-29Added full implementation of simulating a Chipomagdy71-51/+90
2023-11-29Changed Chip structure and added pins which represents the chips input pins ↵omagdy71-4/+6
and output pins and added input and output to reference th ids of those input and output pins
2023-11-29Removed Or and Buffer Gate implementations and added the same logic of ↵omagdy71-49/+74
AndGate to the NotGate
2023-11-29Changed Added pins to AddGate that represents all the and Gate pins and made ↵omagdy71-17/+26
input and output reference pins ids and modified the evaluate function accordingly
2023-11-29Removed uncessary Or and Buffer gatesomagdy71-51/+44
2023-11-27Added dfs traversal of gates graphomagdy71-27/+69
2023-11-27Added the intial design of the logic gate simulatoromagdy71-97/+304
2023-08-18Cleaned the code + added output_layer for displaying outputsomagdy71-27/+29
2023-08-11Added an InputPanel to the leftomagdy71-13/+33
2023-08-10Intial commitomagdy71-0/+111
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-07 23:32:31 +0000