lgsim - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
master	Added some tests for xor and or gates and also added comments to explain how ...	omagdy7	24 months


Age	Commit message	Author	Files	Lines
2023-12-13	Added some tests for xor and or gates and also added comments to explain how ...HEAD master	omagdy7	2	-147/+326
2023-11-29	Added full implementation of simulating a Chip	omagdy7	4	-438/+131
2023-11-29	Changed Chip structure and added pins which represents the chips input pins a...	omagdy7	1	-4/+6
2023-11-29	Removed Or and Buffer Gate implementations and added the same logic of AndGat...	omagdy7	1	-49/+74
2023-11-29	Changed Added pins to AddGate that represents all the and Gate pins and made ...	omagdy7	1	-17/+26
2023-11-29	Removed uncessary Or and Buffer gates	omagdy7	1	-51/+44
2023-11-29	Changed some types definitions	omagdy7	1	-2/+2
2023-11-27	Added dfs traversal of gates graph	omagdy7	4	-65/+467
2023-11-27	Added the intial design of the logic gate simulator	omagdy7	8	-196/+561
2023-08-18	Cleaned the code + added output_layer for displaying outputs	omagdy7	4	-31/+70
[...]