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Diffstat (limited to 'tm4c123gh6pm.h')
| -rw-r--r-- | tm4c123gh6pm.h | 12870 |
1 files changed, 12870 insertions, 0 deletions
diff --git a/tm4c123gh6pm.h b/tm4c123gh6pm.h new file mode 100644 index 0000000..e739436 --- /dev/null +++ b/tm4c123gh6pm.h @@ -0,0 +1,12870 @@ +//*****************************************************************************
+//
+// tm4c123gh6pm.h - TM4C123GH6PM Register Definitions
+//
+// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __TM4C123GH6PM_H__
+#define __TM4C123GH6PM_H__
+
+//*****************************************************************************
+//
+// Interrupt assignments
+//
+//*****************************************************************************
+#define INT_GPIOA 16 // GPIO Port A
+#define INT_GPIOB 17 // GPIO Port B
+#define INT_GPIOC 18 // GPIO Port C
+#define INT_GPIOD 19 // GPIO Port D
+#define INT_GPIOE 20 // GPIO Port E
+#define INT_UART0 21 // UART0
+#define INT_UART1 22 // UART1
+#define INT_SSI0 23 // SSI0
+#define INT_I2C0 24 // I2C0
+#define INT_PWM0_FAULT 25 // PWM0 Fault
+#define INT_PWM0_0 26 // PWM0 Generator 0
+#define INT_PWM0_1 27 // PWM0 Generator 1
+#define INT_PWM0_2 28 // PWM0 Generator 2
+#define INT_QEI0 29 // QEI0
+#define INT_ADC0SS0 30 // ADC0 Sequence 0
+#define INT_ADC0SS1 31 // ADC0 Sequence 1
+#define INT_ADC0SS2 32 // ADC0 Sequence 2
+#define INT_ADC0SS3 33 // ADC0 Sequence 3
+#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1
+#define INT_TIMER0A 35 // 16/32-Bit Timer 0A
+#define INT_TIMER0B 36 // 16/32-Bit Timer 0B
+#define INT_TIMER1A 37 // 16/32-Bit Timer 1A
+#define INT_TIMER1B 38 // 16/32-Bit Timer 1B
+#define INT_TIMER2A 39 // 16/32-Bit Timer 2A
+#define INT_TIMER2B 40 // 16/32-Bit Timer 2B
+#define INT_COMP0 41 // Analog Comparator 0
+#define INT_COMP1 42 // Analog Comparator 1
+#define INT_SYSCTL 44 // System Control
+#define INT_FLASH 45 // Flash Memory Control and EEPROM
+ // Control
+#define INT_GPIOF 46 // GPIO Port F
+#define INT_UART2 49 // UART2
+#define INT_SSI1 50 // SSI1
+#define INT_TIMER3A 51 // 16/32-Bit Timer 3A
+#define INT_TIMER3B 52 // Timer 3B
+#define INT_I2C1 53 // I2C1
+#define INT_QEI1 54 // QEI1
+#define INT_CAN0 55 // CAN0
+#define INT_CAN1 56 // CAN1
+#define INT_HIBERNATE 59 // Hibernation Module
+#define INT_USB0 60 // USB
+#define INT_PWM0_3 61 // PWM Generator 3
+#define INT_UDMA 62 // uDMA Software
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_ADC1SS0 64 // ADC1 Sequence 0
+#define INT_ADC1SS1 65 // ADC1 Sequence 1
+#define INT_ADC1SS2 66 // ADC1 Sequence 2
+#define INT_ADC1SS3 67 // ADC1 Sequence 3
+#define INT_SSI2 73 // SSI2
+#define INT_SSI3 74 // SSI3
+#define INT_UART3 75 // UART3
+#define INT_UART4 76 // UART4
+#define INT_UART5 77 // UART5
+#define INT_UART6 78 // UART6
+#define INT_UART7 79 // UART7
+#define INT_I2C2 84 // I2C2
+#define INT_I2C3 85 // I2C3
+#define INT_TIMER4A 86 // 16/32-Bit Timer 4A
+#define INT_TIMER4B 87 // 16/32-Bit Timer 4B
+#define INT_TIMER5A 108 // 16/32-Bit Timer 5A
+#define INT_TIMER5B 109 // 16/32-Bit Timer 5B
+#define INT_WTIMER0A 110 // 32/64-Bit Timer 0A
+#define INT_WTIMER0B 111 // 32/64-Bit Timer 0B
+#define INT_WTIMER1A 112 // 32/64-Bit Timer 1A
+#define INT_WTIMER1B 113 // 32/64-Bit Timer 1B
+#define INT_WTIMER2A 114 // 32/64-Bit Timer 2A
+#define INT_WTIMER2B 115 // 32/64-Bit Timer 2B
+#define INT_WTIMER3A 116 // 32/64-Bit Timer 3A
+#define INT_WTIMER3B 117 // 32/64-Bit Timer 3B
+#define INT_WTIMER4A 118 // 32/64-Bit Timer 4A
+#define INT_WTIMER4B 119 // 32/64-Bit Timer 4B
+#define INT_WTIMER5A 120 // 32/64-Bit Timer 5A
+#define INT_WTIMER5B 121 // 32/64-Bit Timer 5B
+#define INT_SYSEXC 122 // System Exception (imprecise)
+#define INT_PWM1_0 150 // PWM1 Generator 0
+#define INT_PWM1_1 151 // PWM1 Generator 1
+#define INT_PWM1_2 152 // PWM1 Generator 2
+#define INT_PWM1_3 153 // PWM1 Generator 3
+#define INT_PWM1_FAULT 154 // PWM1 Fault
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000))
+#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004))
+#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008))
+#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C))
+#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010))
+#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014))
+#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418))
+#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000))
+#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004))
+#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008))
+#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C))
+#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010))
+#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014))
+#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418))
+#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524))
+#define GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528))
+#define GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C))
+#define GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530))
+#define GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524))
+#define GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528))
+#define GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C))
+#define GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530))
+#define GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524))
+#define GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528))
+#define GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C))
+#define GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530))
+#define GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524))
+#define GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528))
+#define GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C))
+#define GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530))
+#define GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000))
+#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004))
+#define SSI0_DR_R (*((volatile uint32_t *)0x40008008))
+#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010))
+#define SSI0_IM_R (*((volatile uint32_t *)0x40008014))
+#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018))
+#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C))
+#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020))
+#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024))
+#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000))
+#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004))
+#define SSI1_DR_R (*((volatile uint32_t *)0x40009008))
+#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C))
+#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010))
+#define SSI1_IM_R (*((volatile uint32_t *)0x40009014))
+#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018))
+#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C))
+#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020))
+#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024))
+#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI2)
+//
+//*****************************************************************************
+#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000))
+#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004))
+#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008))
+#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C))
+#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010))
+#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014))
+#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018))
+#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C))
+#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020))
+#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024))
+#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI3)
+//
+//*****************************************************************************
+#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000))
+#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004))
+#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008))
+#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C))
+#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010))
+#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014))
+#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018))
+#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C))
+#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020))
+#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024))
+#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile uint32_t *)0x4000C000))
+#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004))
+#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004))
+#define UART0_FR_R (*((volatile uint32_t *)0x4000C018))
+#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020))
+#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024))
+#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028))
+#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C))
+#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030))
+#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034))
+#define UART0_IM_R (*((volatile uint32_t *)0x4000C038))
+#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C))
+#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040))
+#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044))
+#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048))
+#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4))
+#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8))
+#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0))
+#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile uint32_t *)0x4000D000))
+#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004))
+#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004))
+#define UART1_FR_R (*((volatile uint32_t *)0x4000D018))
+#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020))
+#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024))
+#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028))
+#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C))
+#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030))
+#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034))
+#define UART1_IM_R (*((volatile uint32_t *)0x4000D038))
+#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C))
+#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040))
+#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044))
+#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048))
+#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4))
+#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8))
+#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0))
+#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R (*((volatile uint32_t *)0x4000E000))
+#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004))
+#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004))
+#define UART2_FR_R (*((volatile uint32_t *)0x4000E018))
+#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020))
+#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024))
+#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028))
+#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C))
+#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030))
+#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034))
+#define UART2_IM_R (*((volatile uint32_t *)0x4000E038))
+#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C))
+#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040))
+#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044))
+#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048))
+#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4))
+#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8))
+#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0))
+#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART3)
+//
+//*****************************************************************************
+#define UART3_DR_R (*((volatile uint32_t *)0x4000F000))
+#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004))
+#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004))
+#define UART3_FR_R (*((volatile uint32_t *)0x4000F018))
+#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020))
+#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024))
+#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028))
+#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C))
+#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030))
+#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034))
+#define UART3_IM_R (*((volatile uint32_t *)0x4000F038))
+#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C))
+#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040))
+#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044))
+#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048))
+#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4))
+#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8))
+#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0))
+#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART4)
+//
+//*****************************************************************************
+#define UART4_DR_R (*((volatile uint32_t *)0x40010000))
+#define UART4_RSR_R (*((volatile uint32_t *)0x40010004))
+#define UART4_ECR_R (*((volatile uint32_t *)0x40010004))
+#define UART4_FR_R (*((volatile uint32_t *)0x40010018))
+#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020))
+#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024))
+#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028))
+#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C))
+#define UART4_CTL_R (*((volatile uint32_t *)0x40010030))
+#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034))
+#define UART4_IM_R (*((volatile uint32_t *)0x40010038))
+#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C))
+#define UART4_MIS_R (*((volatile uint32_t *)0x40010040))
+#define UART4_ICR_R (*((volatile uint32_t *)0x40010044))
+#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048))
+#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4))
+#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8))
+#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0))
+#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART5)
+//
+//*****************************************************************************
+#define UART5_DR_R (*((volatile uint32_t *)0x40011000))
+#define UART5_RSR_R (*((volatile uint32_t *)0x40011004))
+#define UART5_ECR_R (*((volatile uint32_t *)0x40011004))
+#define UART5_FR_R (*((volatile uint32_t *)0x40011018))
+#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020))
+#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024))
+#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028))
+#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C))
+#define UART5_CTL_R (*((volatile uint32_t *)0x40011030))
+#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034))
+#define UART5_IM_R (*((volatile uint32_t *)0x40011038))
+#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C))
+#define UART5_MIS_R (*((volatile uint32_t *)0x40011040))
+#define UART5_ICR_R (*((volatile uint32_t *)0x40011044))
+#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048))
+#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4))
+#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8))
+#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0))
+#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART6)
+//
+//*****************************************************************************
+#define UART6_DR_R (*((volatile uint32_t *)0x40012000))
+#define UART6_RSR_R (*((volatile uint32_t *)0x40012004))
+#define UART6_ECR_R (*((volatile uint32_t *)0x40012004))
+#define UART6_FR_R (*((volatile uint32_t *)0x40012018))
+#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020))
+#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024))
+#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028))
+#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C))
+#define UART6_CTL_R (*((volatile uint32_t *)0x40012030))
+#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034))
+#define UART6_IM_R (*((volatile uint32_t *)0x40012038))
+#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C))
+#define UART6_MIS_R (*((volatile uint32_t *)0x40012040))
+#define UART6_ICR_R (*((volatile uint32_t *)0x40012044))
+#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048))
+#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4))
+#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8))
+#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0))
+#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART7)
+//
+//*****************************************************************************
+#define UART7_DR_R (*((volatile uint32_t *)0x40013000))
+#define UART7_RSR_R (*((volatile uint32_t *)0x40013004))
+#define UART7_ECR_R (*((volatile uint32_t *)0x40013004))
+#define UART7_FR_R (*((volatile uint32_t *)0x40013018))
+#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020))
+#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024))
+#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028))
+#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C))
+#define UART7_CTL_R (*((volatile uint32_t *)0x40013030))
+#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034))
+#define UART7_IM_R (*((volatile uint32_t *)0x40013038))
+#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C))
+#define UART7_MIS_R (*((volatile uint32_t *)0x40013040))
+#define UART7_ICR_R (*((volatile uint32_t *)0x40013044))
+#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048))
+#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4))
+#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8))
+#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0))
+#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0)
+//
+//*****************************************************************************
+#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000))
+#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004))
+#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008))
+#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C))
+#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010))
+#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014))
+#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018))
+#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C))
+#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020))
+#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024))
+#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C))
+#define I2C0_MCR2_R (*((volatile uint32_t *)0x40020038))
+#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800))
+#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804))
+#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808))
+#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C))
+#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810))
+#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814))
+#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818))
+#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C))
+#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820))
+#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0))
+#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1)
+//
+//*****************************************************************************
+#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000))
+#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004))
+#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008))
+#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C))
+#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010))
+#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014))
+#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018))
+#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C))
+#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020))
+#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024))
+#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C))
+#define I2C1_MCR2_R (*((volatile uint32_t *)0x40021038))
+#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800))
+#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804))
+#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808))
+#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C))
+#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810))
+#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814))
+#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818))
+#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C))
+#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820))
+#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0))
+#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C2)
+//
+//*****************************************************************************
+#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000))
+#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004))
+#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008))
+#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C))
+#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010))
+#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014))
+#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018))
+#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C))
+#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020))
+#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024))
+#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C))
+#define I2C2_MCR2_R (*((volatile uint32_t *)0x40022038))
+#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800))
+#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804))
+#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808))
+#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C))
+#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810))
+#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814))
+#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818))
+#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C))
+#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820))
+#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0))
+#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C3)
+//
+//*****************************************************************************
+#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000))
+#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004))
+#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008))
+#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C))
+#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010))
+#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014))
+#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018))
+#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C))
+#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020))
+#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024))
+#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C))
+#define I2C3_MCR2_R (*((volatile uint32_t *)0x40023038))
+#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800))
+#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804))
+#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808))
+#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C))
+#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810))
+#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814))
+#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818))
+#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C))
+#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820))
+#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0))
+#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524))
+#define GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528))
+#define GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C))
+#define GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530))
+#define GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524))
+#define |